HARDWARE REDUCES LATENCY TO SUB-MICROSECOND

NanoSpeed, a provider of ultra-fast FPGA products to the trading community, has launched Nano-TG, an ultra-low latency trading gateway.

Nano-TG is easily customizable by NanoSpeed, for example by incorporating client-specific risk checks and changes to protocols.

“FPGA solutions are now an established and competitive component of the trading lifecycle,” said Sanjay Shah, chief technology officer at NanoSpeed. “The ability to execute trades with greater speed reliably and to handle greater volumes is crucial to gaining and maintaining a competitive edge. The need to outpace your competitors is a continuous goal for market participants. Nano-TG provides what is arguably the fastest technical trading solution.”

NanoSpeed provides low latency, highly-robust FPGA-based trading, market data and risk management systems to investment banks, prop traders and hedge funds, as well as exchanges and other financial institutions. It currently has a Tier One bank using it for electronic FX trading, and is also working with proprietary trading companies in Chicago and Singapore, Shah said.

Nano-TG supports multiple asset classes, client connections and market data streams (up to 32 market data streams per physical connection), 20 million messages per second throughput on binary orders, sub-half microsecond wire-to-wire latency, and APIs for a range of functions, including order display, stop trading and back-office feeds for client- and venue-side orders. “Our intellectual property is targeted to provide bespoke trading solutions,” said Sanjay Shah, chief technology officer at NanoSpeed. “We can with whatever processes and system they have, like algorithmic trading API, and enable them to execute orders in less than half a microsecond, which is an order of magnitude faster than today.”

Separately, Argon Design, a design services company specializing in complex digital systems has developed a high performance trading system using a mix of technologies to minimize trading latency.

Working with Arista Network’s Altera FPGA and Intel’s Xeon processors, and using the test harness developed for the Finteligent Trading Technology Community program, the latency measured was reduced by a factor of 25 over pure x86 designs tested by the program. For the measured leg in the test harness, latency was reduced from a previous best of 4,600ns to 176ns for algorithmically generated trades executed to the simulated market.

The enhancement in performance was achieved by providing a fast-path where trades are executed directly by the FPGA under the control of trigger rules processed by the x86 based functions. As market data enters the switch, the Ethernet frame is parsed serially as bits arrive, allowing partial information to be extracted and matched before the whole frame has been received. The latency is reduced further by two additional techniques in the FPGA – inline parsing and pre-emption.

“By levering the work of the Finteligent community we have been able to demonstrate the application of this technology to low latency trading,” said Steve Barlow, chief technology officer of Argon Design. “Critical here has been the use of a mix of technologies and the selection of appropriate tasks best suited to each processor architecture – combining both software and hardware programming.”